1. Field of the Invention
The present invention relates to a pulse signal generator adapted particularly for use in controlling a pulse generation interval with high precision.
2. Description of the Prior Art
It has been known heretofore to employ, for varying a pulse duration, a pulse signal generator where a plurality of stages of delay gates are connected in series to one another so as to transmit an input signal with a time delay. An exemplary pulse signal generator comprises, as shown in a block diagram of FIG. 1, a plurality of stages of delay gates Ga.sub.l -Ga.sub.n, a plurality of multiplexers M.sub.l -M.sub.n-1, and a latch circuit 1. In such circuit configuration including 2.sub.n delay gates Ga, there are required 2n-1 multiplexers. In this example, the delay circuit is composed of 8 delay gates Ga.sub.1 -Ga.sub.8, 7 multiplexers M.sub.1 -M.sub.7 and a latch circuit 1 for latching a digital signal of 3 bits (D.sub.0 - D.sub.2), and an input pulse signal and a delayed pulse signal obtained from such delay circuit are supplied respectively to a set input terminal S and a reset input terminal R of an R-S flip flop 2 so as to generate a pulse signal having a predetermined pulse duration.
In the delay circuit of the constitution shown in FIG. 1, control signals S.sub.0 -S.sub.6 outputted from the latch circuit 1 serve to control the operations of the multiplexers M.sub.1 -M.sub.7 respectively, whereby each of the signals received from input terminals, IN, INB is delayed by a predetermined time. Consequently, fixed delay amounts are accumulated and increased due to passage of the signals through the n multiplexers between the individual delay gates and the output terminal Q.sub.1, thereby prolonging the formable minimum pulse duration. In addition, there exists another disadvantage that the delay errors caused by the multiplexers M.sub.1 -M.sub.7 are integrated in accordance with a numerical increase of the multiplexers through which the signals pass, hence impairing the monotony of the delay characteristic.
In an attempt to solve the above problems for enhancing both the precision and monotony of the pulse duration with another purpose of reducing the formable minimum pulse duration, differential amplifiers DA.sub.1, DA.sub.2, DA.sub.3 ... each composed of a pair of transistors Tr are connected respectively to the delay gates Gb1, Gb2, Gb3 as shown in FIG. 2. And the outputs of the paired transistors Tr of the differential amplifiers are supplied to a cascode amplifier 10, thereby switching on or off a pair of differential amplifier transistors 10a, 10b which constitute the cascode amplifier 10. In this constitution, resistors R1, R2 are connected respectively to the output terminals of such transistors 10a, 10b.
Accordingly, when switching circuits SW1, SW2, SW3 ... are selectively actuated in accordance with a given delay condition to operate one of the aforementioned differential amplifiers DA.sub.1, DA.sub.2, DA.sub.3 ..., then signals OUT and OUTB delayed by a predetermined time with extremely high precision from the input signals can be obtained from the output terminals of the pair of differential amplifier transistors 10a, 10b.
However, when the input signal is delayed in the manner mentioned, there arises a problem that some jitters are caused in an operation performed at a superhigh speed. Suppose now an exemplary case where the output of the delay gate Gb.sub.n in the circuit configuration of FIG. 2 is selected when the switching circuit SW.sub.n is at a high level ("H").
In this state, if the terminal IN is turned from a low level ("L") to a high level ("H") in response to a pulse fed to the input terminal, then the base voltage of the transistor Ti.sub.11 constituting the differential amplifier DA.sub.1 is turned from "L" to "H" after the lapse of the propagation delay time of the delay gate Gb.sub.1. Subsequently the base voltages of the transistors Tr.sub.21, Tr.sub.31 ... Tr.sub.n1 constituting the differential amplifiers DA.sub.2, DA.sub.3 ... are turned sequentially from "L" to "H". In this case, the base voltages of the other transistors Tr.sub.12, Tr.sub.22 ... Tr.sub.n2 are turned from "H" to "L".
At the time of state transition of each transistor Tr, the current for charging the capacity of the base-emitter junction of the transistor Tr comes to flow in the amplifier 10 cascode-connected to the transistor Tr, so that such current appears as noise in the output signals OUT and OUTB.
For example, when the output is transmitted to the cascode amplifier 10 after the switching circuit SW.sub.n is selected upon passage of the input pulse through the n stages of delay circuits, if another pulse is fed to the input terminal, then the latter pulse comes to flow in the resistors R.sub.1, R.sub.2 via the parasitic capacitance of each transistor Tr. Consequently, noise is induced at points C and CB and is thereby superposed on the output waveform of the cascode amplifier 10. As a result, the amplitude of the signal obtained from the output terminals OUT and OUTB becomes different from a predetermined value to eventually bring about a disadvantage of causing jitters.
The reason for occurrence of such jitters will now be described below with reference to FIGS. 3 through 5. FIGS. 3 and 4 show voltage waveforms obtained at points A, AB, C and CB when signals are fed to the input terminals IN and INB, in which FIG. 4 is an enlarged view of a portion proximate to 800 ps. In these waveform charts, I represents a first voltage scale indicative of the potentials at the points A and AB, and II represents a second voltage scale indicative of the potentials at the points C and CB.
As obvious from FIGS. 3 and 4, when an input signal is fed, noise N of 12 mV or so is generated in the vicinity of 800 ps. Due to generation of such noise, as shown in the waveform chart of FIG. 5, the amplitude of the signal becomes different from the normal value to consequently cause a time delay .DELTA.t at the inversion of the signal polarity, hence inducing jitters.
There is known another exemplary pulse signal generator contrived for the purpose of changing a pulse duration, wherein a plurality of stages of delay gates are connected in series to one another to delay an input signal by a predetermined time. In such conventional pulse signal generator, as shown in a block diagram of FIG. 2, one delay circuit comprises a plurality of stages of delay gates Gb.sub.1 -Gb.sub.n+1, differential connection circuits DA.sub.1 -DA.sub.n+1 for transmitting the signal through the delay gates Gb.sub.1 -Gb.sub.n+1 at a predetermined timing to an output circuit 10, and switching circuits SW.sub.1 -SW.sub.n+1 for selectively operating the delay gate Gb.sub.1 -Gb.sub.n+1.
A required number, e.g. 128, of such delay circuits are connected in series to one another, and the switching circuits SW.sub.1, SW.sub.2, SW.sub.3 ... SW.sub.n+1 are selectively actuated in accordance with a given delay condition to operate one of the differential amplifiers DA.sub.1, DA.sub.2, DA.sub.3 ... DA.sub.n+1, whereby the input signal supplied via an input buffer circuit is delayed by a predetermined time with extremely high precision, and the delayed signal is transmitted from output terminals OUT and OUTB of the output circuit 10.
The required number of the delay circuits are connected in series to one another via delay-circuit connecting wires. In such series arrangement of the delay circuits, it is possible to connect the entire delay circuits in a row if the joints of connection are numerically small. However, in the aforementioned exemplary case where a multiplicity (e.g. 128) of the delay circuits are arranged in a pattern layout on a semiconductor chip, a linear or straight arrangement is not achievable. Therefore, when forming series connection of multiple delay circuits, it is customary to employ such a pattern layout as illustrated in FIG. 6 where the delay circuits are arranged in a plurality, e.g. four, by 32 stages.
In such arrangement divided into a plurality of stages, no problem is existent as far as the series connection itself is concerned, but the delay-circuit connecting wire 22 in each turned portion is rendered longer than that in any other portion. Consequently the wiring capacity in the turned portion becomes far greater than that in any other straight portion to eventually bring about a disadvantage that the delay time linearity is deteriorated in the turned portion 23.